본문으로 건너뛰기

Synthesis and Analysis of Timing Constraints for Real-Time Embedded Systems using Modular TER nets

· 약 1분
이우진
담당교수
Ho Kyoung Lee

WSEAS Transactions on Computers (ISSN : 1109-2750), Vol. 6, No. 5, pp. 741-748, May 2007.